An integrated logical and physical design flow for deep submicron circuits

This paper presents a set of techniques and a new design flow to be used in the synthesis of high-performance deep-submicron logic circuits. The design flow consists of circuit partitioning into tree-like clusters, floorplanning, global routing, and timing analysis/budgeting steps, followed by simultaneous technology mapping and linear placement of each cluster. The strength of this approach lies in the dynamic programming-based algorithms used in performing simultaneous technology mapping and linear placement of the logic clusters. The two algorithms we propose, one for exact total (gate plus routing) area minimization and the other for total (gate plus routing) delay minimization, generate a set of non-inferior solutions for each cluster enabling designers to perform trade-offs between total-area and total-delay. Experimental results on a large number of MCNC benchmarks prove the effectiveness of the proposed flow.